DSPIC30F3011-30I/P DIP40 - 4902475 _{Yêu thích}

DSPIC30F3011-30I/P DIP40

http://ww1.microchip.com/downloads/en/devicedoc/70141f.pdf

High-Performance Modified RISC CPU:

• Modified Harvard Architecture

• C Compiler Optimized Instruction Set Architecture with Flexible Addressing modes

• 83 Base Instructions

• 24-bit Wide Instructions, 16-bit Wide Data Path

• 24 Kbytes On-Chip Flash Program Space (8K instruction words)

• 1 Kbyte of On-Chip Data RAM

• 1 Kbyte of Nonvolatile Data EEPROM

• 16 x 16-bit Working Register Array

• Up to 30 MIPs Operation: - DC to 40 MHz external clock input - 4 MHz-10 MHz oscillator input with PLL active (4x, 8x, 16x)

• 29 Interrupt Sources - 3 external interrupt sources - 8 user-selectable priority levels for each interrupt source - 4 processor trap sources