dsPic30F4013-30I/P DIP40 - 4902473 _{Yêu thích}

dsPic30F4013-30I/P DIP40

http://ww1.microchip.com/downloads/en/devicedoc/70138c.pdf

High-Performance Modified RISC CPU:

• Modified Harvard architecture

• C compiler optimized instruction set architecture

• Flexible addressing modes

• 84 base instructions

• 24-bit wide instructions, 16-bit wide data path

• Up to 48 Kbytes on-chip Flash program space

• 2 Kbytes of on-chip data RAM

• 1 Kbyte of non-volatile data EEPROM

• 16 x 16-bit working register array

• Up to 30 MIPs operation: - DC to 40 MHz external clock input - 4 MHz-10 MHz oscillator input with PLL active (4x, 8x, 16x)

• Up to 33 interrupt sources: - 8 user selectable priority levels - 3 external interrupt sources - 4 processor traps DSP Features:

• Dual data fetch • Modulo and Bit-reversed modes

• Two 40-bit wide accumulators with optional saturation logic

• 17-bit x 17-bit single cycle hardware fractional/ integer multiplier

• All DSP instructins are single cycle - Multiply-Accumulate (MAC) operation

• Single cycle ±16 shift